1. Field of the Invention
The present invention is relates to a package structure and forming method which is applied for semiconductor manufacture, and more particularly is related to a chip package structure and a package method.
2. Description of the Prior Art
The semiconductor technology is well developed and grown up very fast. Because the microlized semiconductor dice are required to include more functions, the semiconductor dice are necessary to have more input/output (I/O) pads. The density of the metal pins is higher day after day. Therefore, the previous lead package technology is not compatible for dice with high density of metal pins. A Ball Grid Array (BGA) package method is used for dices with high density of metal pins. The BGA package method is not only suitable for using in dices with high density of metal pins, but also the solder balls is not easy to be damaged and out of shape.
Because the 3C products, such as cell phone, personal digital assistant (PDA), or MP3 player, are more and more popular in the market, there are more and more complicated chips installed in a very tiny space. In order to solve the microlized problems, a wafer lever package (WLP) technology is developed. The WLP technology is able to package the dice before sawing them to be several chips. U.S. Pat. No. 5,323,051 discloses a WLP technology. However, when the pads on the active surface of the chips are increased and the interval between the pads is become smaller, the WLP technology will cause the signal overlapped or interrupted problems. So, when the chip is become further smaller, the previous package methods are not good enough to use.
In order to solve the problem described above, U.S. Pat. No. 7,196,408 discloses that a wafer is tested and sawed in semiconductor manufacture and put the good dice in another carrier board to do the package process. Therefore, the pads on the dice are able to be separated with good interval. For example a fan out technology is used, it is able to solve the small interval problem but it may cause the signal overlapped or signal interrupt problems.
Nevertheless, in order to let the semiconductor chips have smaller and thinner package structures, before sawing the dices, the wafer will do a thin process first, such as backside lapping process to thin the wafer in 2˜20 mils, and the wafer is sawed to be several pieces of chips. After the thin process is done, the dices are put on another carrier board and a molding process is used to encapsulate the chip to be a package structure. Because the chip is very thin, the package structure is also very thin. Therefore, when the package structure is left from the carrier board, the package structure would be out of shape and it would cause the difficulty to do the sawing process.
After sawing the wafer, because the dice are put on another carrier board, the size of the new carrier board is larger than the original carrier board, the ball mounting process is hard for the solder ball to be installed at the exact location and the reliability of the package structure is reduced.
Besides, in the package procedure, the manufacture equipment will generate more pressure in the dice during the ball mounting process. Because of the material of the balls, the resistance between the balls and the solder pads will be become higher than usual and it would affect the function of the chips.